A 0.65-ns, 72-kb ECL-CMOS RAM Macro for a 1-Mb SRAM

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Description

An ultrahigh-speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65-ns address-access time, 0.80-ns write-pulse width, and 30.24-μm^2 memory cells has been developed using 0.3-μm BiCMOS technology. Two key techniques for achieving ultrahigh speed are an ECL decoder/driver circuit with a BiCMOS inverter and a write-pulse generator with a replica memory cell. These circuit techniques can reduce access time and write-pulse width of the 72-kb RAM macro to 71% and 58% of those of RAM macros with conventional circuits. In order to reduce crosstalk noise for CMOS memory-cell arrays driven at extremely high speeds, a twisted bit-line structure with a normally on MOS equalizer is proposed. These techniques are especially useful for realizing ultrahigh-speed, high-density SRAM's, which have been used as cache and control storages in mainframe computers.

Journal

  • IEICE transactions on electronics

    IEICE transactions on electronics 78 (6), 739-747, 1995-06-20

    The Institute of Electronics, Information and Communication Engineers

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Details 詳細情報について

  • CRID
    1573105977084663040
  • NII Article ID
    110006388704
  • NII Book ID
    AA10826283
  • ISSN
    09168524
  • Text Lang
    en
  • Data Source
    • CiNii Articles

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