Design and Chip Fabrication of Seal Impression Matching LSI

  • SHRATAKI Akiko
    Department of Electronic Information System Engineering, Shibaura Institute of Technology
  • SUZUKI Satoru
    Department of Electronic Information System Engineering, Shibaura Institute of Technology
  • UEDA Kazuhiro
    Department of Electronic Information System Engineering, Shibaura Institute of Technology

Bibliographic Information

Other Title
  • 印鑑照合処理専用LSIの設計・試作の検討

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Description

In Japan seal impression is regularly used instead of a signature.Seal verification is necessary for identifying a person or permitting an approval for financial purposes.Seal impressions are verified by computer software but it takes much amount of time.In order to reduce the processing time for matching of seal impressions, hardware implementation of the process hasbeenstudied.A hardware architecture and its cicuits have been designed, verified by using a logic simulator, and followed by layout design.This report describes the architecture of the seal matching hardware, the verification results with PLDs and the chip prototyping results.

Journal

  • Technical report of IEICE. ICD

    Technical report of IEICE. ICD 97 (579), 25-30, 1998-03-06

    The Institute of Electronics, Information and Communication Engineers

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Details 詳細情報について

  • CRID
    1573105977274090496
  • NII Article ID
    110003316752
  • NII Book ID
    AN10013276
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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