Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinational Circuits Based on Partition Theory (Special Issue on Multiple-Valued Logic)

  • Tamaki Saneaki
    Graduate School of Engineering, Tohoku University
  • Kameyama Michitaka
    Graduate School of Information Sciences, and Faculty of Engineering, Tohoku University
  • Higuchi Tatsuo
    Graduate School of Information Sciences, and Faculty of Engineering, Tohoku University

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Description

Design of locally computable combinational circuits is a very important subject to implement high-speed compact arithmetic and logic circuits in VLSI systems. This paper describes a multiple-valued code assignment algorithm for the locally computable combinational circuits, when a functional specification for a unary operation is given by the mapping relationship between input and output symbols. Partition theory usually used in the design of sequential circuits is effectively employed for the fast search for the code assignment problem. Based on the partition theory, mathematical foundation is derived for the locally computable circuit design. Moreover, for permutation operations, we propose an efficient code assignment algorithm based on closed chain sets to reduce the number of combinations in search procedure. Some examples are shown to demonstrate the usefulness of the algorithm.

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Details 詳細情報について

  • CRID
    1573105977301469056
  • NII Article ID
    110003219595
  • NII Book ID
    AA10826272
  • ISSN
    09168532
  • Text Lang
    en
  • Data Source
    • CiNii Articles

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