Statistical Gate-Delay Modeling with Intra-Gate Variability

OKADA Kenichi, YAMAOKA Kento, ONODERA Hidetoshi

Statistical Gate-Delay Modeling with Intra-Gate Variability

参考文献16件

OKADA Kenichi

Department of Communications and Computer Engineering, Kyoto University
YAMAOKA Kento

Department of Communications and Computer Engineering, Kyoto University
ONODERA Hidetoshi

Department of Communications and Computer Engineering, Kyoto University

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説明

This paper proposes a model to calculate statistical gate-delay variation caused by intra-chip and inter-chip variabilities. The variation of each gate delay directly influences the circuit-delay variation, so it is important to characterize each gate-delay variation accurately. Every transistor in a gate affects transient characteristics of the gate, so it is indispensable to consider an intra-gate variability for the modeling of gate-delay variation. This effect is not captured in a statistical delay analysis reported so far. Our model considers the intra-gate variability by sensitivity constants. We evaluate our modeling accuracy, and we show some simulated results of a circuit delay variation.

収録刊行物

IEICE transactions on fundamentals of electronics, communications and computer sciences

IEICE transactions on fundamentals of electronics, communications and computer sciences 86 (12), 2914-2922, 2003-12-01

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