Redundant Design for Wallace Multiplier

NAMBA Kazuteru, ITO Hideo

To increase the yield of data processing circuits such as adders and logic operation circuits, the bit-slice reconfiguration design has been proposed as an efficient redundant technology for defect-tolerance. Wallace multipliers are a well-known class of high-speed parallel multipliers. Unfortunately, the bit-slice reconfiguration design is not applicable to Wallace multipliers because Wallace multipliers do not have regular bit-slice structure. Therefore, redundant designs for Wallace multipliers have been regarded impossible. This paper proposes a redundant design for Wallace multipliers. In order to design redundant Wallace multipliers, first, 2n heterogeneous slices are considered in a non-redundant n×n Wallace multiplier. The proposed redundant Wallace multipliers contain reconfigurable slices which can play the role of both i-th and (i+1)-th slices. Since the i-th slice has a similar structure to the (i+1)-th slice, the reconfigurable slice is not much larger than the i-th slice. This paper also shows a repair procedure for the proposed design. This paper evaluates the proposed design from the viewpoint of the yield, area, effective yield and delay time. For example, the yield of a 32×32 Wallace multiplier increases from 0.30 to 0.41 by applying the proposed design while the area increases by a factor of 1.21.

Redundant Design for Wallace Multiplier

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