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Mechanism of gate leakage current generation in GaAs HIGFET
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- TAKATANI Shinichiro
- Central Research Laboratory
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- MATSUMOTO Hidetoshi
- Central Research Laboratory
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- SHIGETA Junji
- Central Research Laboratory
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- YAMASHITA Tomoko
- Device Development Center
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- OSHIKA Katsushi
- Semiconductor & Integrated Circuit Division
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- FUKUI Munetoshi
- Device Development Center
Bibliographic Information
- Other Title
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- GaAs HIGFETにおけるゲートリーク電流発生機構
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Description
A phenomenon is observed in an i-AlGaAs/n-GaAs HIGFET that the gate leakage current increases under a reverse gate-drain bias. Detailed analysis of the degradation phenomena and characterization of the insulator/semiconductor(I/S) interface using a MIS diode show that this degradation is due to hole trap at the I/S interface near the drain edge of the gate electrode. The degradation is eliminated by CF_4 plasma treatment. The effect of the treatment is explained from an XPS analysis as due to the removal of As_2S_3, which is formed on the GaAs surface in the WSi gate etching process using SF_6/CHF_3.
Journal
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- IEICE technical report. Electron devices
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IEICE technical report. Electron devices 96 (353), 27-34, 1996-11-09
The Institute of Electronics, Information and Communication Engineers
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Details 詳細情報について
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- CRID
- 1573387452170895104
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- NII Article ID
- 110003200061
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- NII Book ID
- AN10012954
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- Text Lang
- ja
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- Data Source
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- CiNii Articles