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Performance of p-channel HJFET with Selectively Grown Contact Layers
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- FURUHATA Naoki
- NEC Opto-Electronics Research Laboratories
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- ASAI Shuji
- NEC ULSI Device Development Laboratories
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- MAEDA Tadashi
- NEC Opto-Electronics Research Laboratories
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- FUJII Masahiro
- NEC Opto-Electronics Research Laboratories
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- OHNO Yasuo
- NEC Opto-Electronics Research Laboratories
Bibliographic Information
- Other Title
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- ソースドレイン領域選択成長pチャネルHJFETの試作と評価
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Description
This paper reports on performance of 0.5μm gate p-channel HJFET for GaAs complementary ICs. The device structure consists of i-Al_<0.75>Ga_<0.25>As barrier layer, p-GaAs(2×10^<18>cm^<-3>) channel layer and p^+-GaAs(2×10^<20>cm^<-3>) contact layers. The contact layers were selectively grown by MOMBE. This device achieved gm_<max> of 40mS/mm, Vf of -0.9V, BVg of 6.0V, f_T of 6.8GHz and fmax of 7.0GHz. To estimate GaAs complementary ICs performances, a delay time and power consumption were simulated by SPICE. As a result, t_<pd> of 120ps and 0.09μW/MHz/gate power consumption at V_<DD> of 1.0V were obtained.
Journal
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- Technical report of IEICE. ICD
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Technical report of IEICE. ICD 97 (111), 81-87, 1997-06-20
The Institute of Electronics, Information and Communication Engineers
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Details 詳細情報について
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- CRID
- 1573387452251405440
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- NII Article ID
- 110003316613
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- NII Book ID
- AN10013276
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- Text Lang
- ja
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- Data Source
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- CiNii Articles