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A 3.3V 32Mbit Page Mode MASK ROM with Low Power Sensing Scheme
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- KOUCHI Shuichiro
- Memory IC Engineering Center Tenri IC Group, SHARP Corporation
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- MATSUYAMA Ryusuke
- Memory IC Engineering Center Tenri IC Group, SHARP Corporation
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- HOTTA Yasuhiro
- Memory IC Engineering Center Tenri IC Group, SHARP Corporation
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- OKADA Mikiro
- Memory IC Engineering Center Tenri IC Group, SHARP Corporation
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- TSUGITA Hirosi
- Memory IC Engineering Center Tenri IC Group, SHARP Corporation
Bibliographic Information
- Other Title
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- 低電力32Mビット・ページモードマスクROM
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Description
A 32Mbit Page Mode MASK ROM is developed without significant penalty of increasing chip size and power consumption. A new bank select memory architecture, a new page mode sensing scheme and a burst mode decoder are developed to realize high speed and low power operation. Typical burst mode access time of 2Qns and operating current of 25mA are obtained using a CMOS single-poly single-metal process without affecting distinctive characteristics of MASK ROM.
Journal
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- Technical report of IEICE. SDM
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Technical report of IEICE. SDM 96 (226), 85-90, 1996-08-23
The Institute of Electronics, Information and Communication Engineers
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Details 詳細情報について
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- CRID
- 1573387452256482560
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- NII Article ID
- 110003309670
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- NII Book ID
- AN10013254
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- Text Lang
- ja
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- Data Source
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- CiNii Articles
