Method of Estimating Gate Delay for High-frequency CMOS Circuits Using Laplace Transform Solution

Bibliographic Information

Other Title
  • Laplace領域の解析的解法による高速高精度ゲートディレイ計算方法

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Description

In this paper, a new estimating method of gate delay for high-frequency CMOS logic circuits is proposed. Using the Laplace transform solution of the nodal equation based on equivalent circuits of the gate, this method can predict the delay as accurately as a circuit simulation and at faster than 1000 times the speed.

Journal

Details 詳細情報について

  • CRID
    1573668926893244416
  • NII Article ID
    110002676011
  • NII Book ID
    AA11451459
  • ISSN
    09196072
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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