A Fast and Accurate Method of Redesigning Analog Subcircuits for Technology Scaling
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- FUNABA Seiji
- Semiconductor & Integrated Circuits Group, Hitachi, Ltd.
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- KITAGAWA Akihiro
- Semiconductor & Integrated Circuits Group, Hitachi, Ltd.
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- TSUKADA Toshiro
- Semiconductor & Integrated Circuits Group, Hitachi, Ltd.
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- YOKOMIZO Goichi
- Semiconductor & Integrated Circuits Group, Hitachi, Ltd.
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説明
In this paper, we present an efficient approach for technology scaling of MOS analog circuits by using circuit optimization techniques. Our new method is based on matching equivalent circuit parameters between a previously designed circuit and the circuit undergoing redesign. This method has been applied to a MOS operational amplifier. We were able to produce a redesigned circuit with almost the same performance in under 4 hours, making this method 5 times more efficient than conventional methods.
収録刊行物
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- IEICE transactions on fundamentals of electronics, communications and computer sciences
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IEICE transactions on fundamentals of electronics, communications and computer sciences 82 (2), 341-347, 1999-02-25
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詳細情報 詳細情報について
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- CRID
- 1573668927255886336
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- NII論文ID
- 110003216551
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- NII書誌ID
- AA10826239
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- ISSN
- 09168508
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- 本文言語コード
- en
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- データソース種別
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- CiNii Articles