A Fast and Accurate Method of Redesigning Analog Subcircuits for Technology Scaling

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説明

In this paper, we present an efficient approach for technology scaling of MOS analog circuits by using circuit optimization techniques. Our new method is based on matching equivalent circuit parameters between a previously designed circuit and the circuit undergoing redesign. This method has been applied to a MOS operational amplifier. We were able to produce a redesigned circuit with almost the same performance in under 4 hours, making this method 5 times more efficient than conventional methods.

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詳細情報 詳細情報について

  • CRID
    1573668927255886336
  • NII論文ID
    110003216551
  • NII書誌ID
    AA10826239
  • ISSN
    09168508
  • 本文言語コード
    en
  • データソース種別
    • CiNii Articles

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