A Delay Calculator System for Deep Submicron Design

5 References
  • OHSHIMA Takayuki
    ULSI Systems Development Laboratories, System LSI Operations Unit, NEC
  • SAITO Toshiyuki
    ULSI Systems Development Laboratories, System LSI Operations Unit, NEC
  • FUJITA Yoko
    ULSI Systems Development Laboratories, System LSI Operations Unit, NEC
  • MINODA Yukio
    ULSI Systems Development Laboratories, System LSI Operations Unit, NEC
  • NAKAYA Takashi
    ULSI Systems Development Laboratories, System LSI Operations Unit, NEC

Bibliographic Information

Other Title
  • ディープサブミクロンに対応した遅延計算システム

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Description

As CMOS technologies continue to improve, the feature sizes of transistors and interconnect wiring are getting into the deep submicron region. With this trend, the R per unit length and the C per unit length of metal interconnect increase respectively, while the gate size decreases. For the above reasons, the overall delay is attributed to the interconnect delay rather than gate delay. According to the RC shielding, the calculation of the gate delay needs the effective capacitance. In this paper, a new delay calculation system and the delay calculation flow is proposed, in which the interconnect delay is calculated with original RC circuit simulator, and the gate delay is calculated with the model proposed in [3], which can consider the effective capacitance.

Journal

  • Technical report of IEICE. VLD

    Technical report of IEICE. VLD 98 (624), 43-49, 1999-03-03

    The Institute of Electronics, Information and Communication Engineers

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Keywords

Details 詳細情報について

  • CRID
    1573950402106789504
  • NII Article ID
    110003294884
  • NII Book ID
    AN10013323
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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