A 2.4-Gb/s CMOS Clock Recovering 1:8 Demultiplexer

7 References
  • SODA M.
    Opto-Electronics Research Labs., NEC Corporation
  • TANABE A.
    Microelectronics Research Labs., NEC Corporation
  • TEZUKA H.
    Opto-Electronics Research Labs., NEC Corporation
  • SHIOIRI S.
    Opto-Electronics Research Labs., NEC Corporation
  • TOGO M.
    ULSI Device Development Labs., NEC Corporation
  • TAMURA T.
    ULSI Device Development Labs., NEC Corporation
  • YOSHIDA K.
    ULSI Device Development Labs., NEC Corporation
  • FURUKAWA A.
    Microelectronics Research Labs., NEC Corporation

Bibliographic Information

Other Title
  • 2.4Gb/s CMOSクロックリカバリ機能付き1:8DMUX

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Description

A 2.4-Gb/s clock recovering 1:8 demultiplexer with extremely low power consumption, has been developed using 0.15μm gate CMOS technology. For higher operation speed, a clock recovering is achieved by a PLL, synchronizing with half the period of input data. A newly designed phase comparator in the PLL compares the phase differences between the data and the half clock. The core circuit of the IC dissipates only 87 mW with 2-V supply voltage.

Journal

  • Technical report of IEICE. ICD

    Technical report of IEICE. ICD 97 (110), 23-28, 1997-06-19

    The Institute of Electronics, Information and Communication Engineers

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Details 詳細情報について

  • CRID
    1573950402203286400
  • NII Article ID
    110003316594
  • NII Book ID
    AN10013276
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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