-
- ENDOH Tetsuo
- Research Institute of Electrical Communication, Tohoku University
-
- NAKAMURA Tairiku
- Research Institute of Electrical Communication, Tohoku University
-
- MASUOKA Fujio
- Research Institute of Electrical Communication, Tohoku University
この論文をさがす
説明
A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) is analyzed. First, the new gate oxide capacitance model and the new threshold voltage model of FD-SGT are proposed. It is shown that the gate oxide capacitance per unit area increases with scaling down the silicon pillar's diameter. It is newly found that the threshold voltage decreases with scaling down the silicon pillar's diameter, because the gate oxide electric fields increase with increasing gate oxide capacitance. Next, by using the proposed models, the new current-voltage characteristics equation of FD-SGT is analytically formulated for the first time. In comparison with the results of the three-dimensional (3D) device simulator, the results of the new threshold voltage model show good agreement within 0.012V error in maximum. The results of the newly formulated current-voltage characteristics also show good agreement within 1.4% average error. The results of this work make it possible to theoretically clear the device designs of FD-SGT and show the new viewpoints for future ULSI's with SGT.
収録刊行物
-
- IEICE transactions on electronics
-
IEICE transactions on electronics 80 (7), 905-909, 1997-07-25
一般社団法人電子情報通信学会
- Tweet
詳細情報 詳細情報について
-
- CRID
- 1573950402231794304
-
- NII論文ID
- 110003211288
- 10000053413
-
- NII書誌ID
- AA10826283
-
- ISSN
- 09168524
-
- 本文言語コード
- en
-
- データソース種別
-
- CiNii Articles
