Single-Cycle-Accessible Two-Level Cache Architecture

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Other Title
  • シングルサイクルアクセス可能な二階層キャッシュアーキテクチャ(省エネ,組込技術とネットワークに関するワークショップETNET2009)

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Description

A small L0-cache located between an MPU core and an L1-cache is widely used in embedded processors for reducing the energy consumption of memory subsystems. Since the L0-cache is small, if there is a hit, the energy consumption will be reduced. On the other hand, if there is a miss, at least one extra cycle is needed to access the L1-cache. This degrades the processor performance. Single-cycle-accessible Two-level Cache (STC) architecture proposed in this paper can resolve the problem in the conventional L0-cache based approach. Both a small L0 and a large L1 caches in our STC architecture can be accessed from an MPU core within a single cycle. A compilation technique for effectively utilizing the STC architecture is also presented in this paper. Experiments using several benchmark programs demonstrate that our approach reduces the energy consumption of memory subsystems by 64% in the best case and by 41% on an average without any performance degradation compared to the conventional L0-cache based approach.

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Details 詳細情報について

  • CRID
    1573950402297399040
  • NII Article ID
    110007226226
  • NII Book ID
    AA12149313
  • ISSN
    09196072
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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