Control Gate Length, Spacing and Stacked Layer Number Design for BiCS NAND Flash Memory

  • Hirasawa Reo
    Department of Electrical, Electronic, and Communication Engineering, Faculty of Science and Engineering, Chuo University
  • Miyaji Kousuke
    Department of Electrical, Electronic, and Communication Engineering, Faculty of Science and Engineering, Chuo University
  • Takeuchi Ken
    Department of Electrical, Electronic, and Communication Engineering, Faculty of Science and Engineering, Chuo University

Bibliographic Information

Other Title
  • BiCS型立体構造NANDフラッシュメモリーにおけるゲート長、ゲート間隔及び積層数の設計指針

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Description

3D NAND flash memories are promising for further reduction of the bit cost. In this paper, scaling and device design for 3D-stackable NAND (3D NAND) flash memory are investigated. Control gate length (Lg) and gate spacing (Lspace) are varied as a parameter. The gate pitch that satisfies the requirements for electrical characteristic is examined. Simulations reveal that Lg=Lspace=20nm (40nm gate pitch) is achievable for BiCS type 3D NAND with the 90nm diameter hole. If the number of stacked layers is 18 with the gate pitch of 40nm, the effective cell size of the 3D NAND corresponds to that of 15nm planar NAND technology.

Journal

  • Technical report of IEICE. ICD

    Technical report of IEICE. ICD 112 (365), 57-, 2012-12-10

    The Institute of Electronics, Information and Communication Engineers

Keywords

Details 詳細情報について

  • CRID
    1573950402675686400
  • NII Article ID
    110009667347
  • NII Book ID
    AN10013276
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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