A 1 V Phase Locked Loop with Leakage Compensation in 0.13μm CMOS Technology

被引用文献1件 参考文献7件
  • CHUANG Chi-Nan
    Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University
  • LIU Shen-Iuan
    Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University

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説明

In deep sub-micrometer CMOS process, owing to the thin gate oxide and small subthreshold voltage, the leakage current becomes more and more serious. The leakage current has made the impact on phaselocked loops (PLLs). In this paper, the compensation circuits are presented to reduce the leakage current on the charge pump circuit and the MOS capacitor as the loop filter. The proposed circuit has been fabricated in 0.13-μm CMOS process. The power consumption is 3 mW and the die area is 0.27×0.3mm^2.

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詳細情報 詳細情報について

  • CRID
    1574231876681458048
  • NII論文ID
    110004656670
  • NII書誌ID
    AA10826283
  • ISSN
    09168524
  • 本文言語コード
    en
  • データソース種別
    • CiNii Articles

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