A 2.6-ns Wave-Pipelined CMOS SRAM with Dual-Sensing-Latch Circuits

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Description

The dual-sensing-latch circuit proposed here can solve the synchronization problem of the conventional wave-pipelined SRAM, and the proposed source-biased self-resetting circuit reduces both the cycle and access time of cache SRAM's. A 16-kb SRAM using these circuit techniques was designed, and was fabricated with 0.25-μm CMOS technology. Simulation results indicate that this SRAM has a typical clock access time of 2.6ns at 2.5-V supply voltage and a worst minimum cycle time of 2.6ns.

Journal

  • IEICE transactions on electronics

    IEICE transactions on electronics 78 (6), 735-738, 1995-06-20

    The Institute of Electronics, Information and Communication Engineers

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Details 詳細情報について

  • CRID
    1574231876991493632
  • NII Article ID
    110006388703
  • NII Book ID
    AA10826283
  • ISSN
    09168524
  • Text Lang
    en
  • Data Source
    • CiNii Articles

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