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A Scheduling Method for Pipelined Datapaths Considering Register-to-Register Data Transfers
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- HARASHIMA Katsumi
- Faculty of Engineering, University of Osaka Prefecture
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- KOMI Hironori
- Hitachi ltd.
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- FUKUNAGA Kunio
- Faculty of Engineering, University of Osaka Prefecture
Bibliographic Information
- Other Title
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- レジスターレジスタ間データ転送を考慮したパイプライン方式データパスのスケジューリング法
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Description
In high level synthesis, scheduling is an important stage which assigns each operation appeared in a data flow graph to a specific control step, of which results influence the design quality directly. This paper describes a scheduling approach for pipelined datapaths. Since no previous approach estimates the interconnection cost between registers (register-to-register cost), our approach introduces a datapath model with the interconnection between registers across buses, and minimizes the total hardware cost including the register-to-register cost with Integer Linear Programming approaches. Consequently the proposed approach can estimate the hardware cost exactly in the scheduling phase.
Journal
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- Technical report of IEICE. VLD
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Technical report of IEICE. VLD 95 (420), 7-12, 1995-12-14
The Institute of Electronics, Information and Communication Engineers
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Details 詳細情報について
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- CRID
- 1574231877083208064
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- NII Article ID
- 110003294664
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- NII Book ID
- AN10013323
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- Text Lang
- ja
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- Data Source
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- CiNii Articles
