Control structure of an MPEG-2 video encoder LSI for HDTV

Bibliographic Information

Other Title
  • HDTV対応MPEG-2エンコーダLSIの制御構成

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Description

We developed a single chip MPEG-2 encoder, called SuperENC. The structural feature is that the chip has a systolic array and an SIMD processor for motion estimation/compensation and a processor-type SDRAM interface unit, called SDIF, with prioritizing the transmission for external SDRAMs over the internal coding operation. The SPMD-type cooperation using the nine chips deals with HDTV encoding requiring for high operation capability more than 50 GOPS and high-speed data transmission of 2 GB/s. This SuperENC has high function and control flexibility obtained by adequate division of control work for a RISC controller, the SIMD and the SDIF on the chip.

Journal

  • Technical report of IEICE. FTS

    Technical report of IEICE. FTS 101 (3), 65-72, 2001-04-06

    The Institute of Electronics, Information and Communication Engineers

Keywords

Details 詳細情報について

  • CRID
    1574231877096600320
  • NII Article ID
    110003194443
  • NII Book ID
    AN10012998
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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