Implementation of repetitive controllers subject to fractional delays

Repetitive schemes represent a very attractive solution for harmonics compensation, as they are simple to implement and the computational effort is reduced. Their implementation, usually performed in digital form, involves the interconnection of a single delay line or a simple array of delay lines. In discrete time domain, a delay line is implemented using a given number of memory locations, where samples are allocated and released after a specific number of sampling periods (discrete delay) equivalent to the delay time. This discrete delay is obtained as the ratio between the sampling period and the required delay time. The problem arises whenever the delay time is a noninteger multiple of the sampling period, in this case the discrete delay is a real positive number having a fractional part. This issue is referred in signal processing literature as fractional delay. This paper presents a solution for the practical implementation of repetitive schemes where the delay lines are subject to the fractional delay issue. The solution consists in the introduction, on each delay line, of an additional filter aimed to approximate such a fractional delay. This filter has the structure of a finite impulse response (FIR) filter, and thus, it is referred as FIR fractional delay (FIR-FD) filter. Its design follows a Lagrange interpolation technic, which relays in explicit formulae for the computation of the coefficients of the FIR filter. In particular, the present paper is focused in the repetitive scheme proposed in [11] for compensation of harmonics 6l ± 1 (l = 0, 1, 2, ...∞) of the fundamental frequency . Numerical results are presented to confirm the benefits of the proposed scheme. Experiments are in process and the results will be available in the final version of the paper.