A 100-Gbps low-power PRBS generator based on a half-rate-clock architecture using InP HBTs
説明
A new architecture using a half-rate clock for pseudo-random-bit-sequence (PRBS) generator has been devised for high-speed and low-power operation. For proof of concept, a 2 7 -1 PRBS generator IC was designed and fabricated with 290-GHz-f T InP HBT technology. The PRBS generator operates up to 100 Gbps with a low power consumption of 955 mW, leading to a record figure-of-merit of 1.42 mW·Gbps -1 . This circuit can provide a clear waveform with a very low RMS jitter of less than 500 fs in the whole operation range.
収録刊行物
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- 2014 IEEE MTT-S International Microwave Symposium (IMS2014)
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2014 IEEE MTT-S International Microwave Symposium (IMS2014) 1-3, 2014-06-01
IEEE
