A hardware/software partitioning algorithm for designing pipelined ASIPs with least gate counts
説明
This paper introduces a new HW/SW partitioning algorithm used in automating the instruction set processor design for pipelined ASIP (application specific integrated processor). The partitioning problem is formalized as a combinatorial optimization problem that partitions the operations into hardware and software so that the HW cost (gate count) of the designed pipelined ASIP is minimized under given execution cycle and power consumption constraints. A branch-and-bound algorithm with proposed lower bound functions is used to solve the presented formalization in the PEAS-I system. The experimental results show that the proposed method is found to be effective and efficient.
収録刊行物
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- Proceedings of the 33rd annual conference on Design automation conference - DAC '96
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Proceedings of the 33rd annual conference on Design automation conference - DAC '96 527-532, 1996-01-01
ACM Press
