Compact modeling of power devices embedded in advanced low-power CMOS circuits

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A compact model for power devices with advanced technology is developed which considers the geometry dependent potential distribution along the device explicitly. The model solves key potential nodes within the device iteratively to realize accurate modeling of the underlap, which occurs in HV\MOSFETs, as well as of the non-monotonous potential-distribution region. With use of the developed model it is verified that the suppression of the switching loss can be done by optimizing the device geometry, because all geometry parameters are explicitly considered in this modeling.

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