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Description
This paper proposes an instruction scheduling technique to reduce power consumed for off-chip driving. The technique minimizes the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and a scheduling algorithm is also presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithm.
Journal
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- Proceedings Design, Automation and Test in Europe
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Proceedings Design, Automation and Test in Europe 855-860, 2002-11-27
IEEE Comput. Soc