Pb-free bumping for high-performance SoCs
説明
We have already developed the eutectic Sn-Ag solder bumping process by alloying Ag/Sn electroplated metal stacks. Alloying electroplated Ag/Cu/Sn stacks has been also a successful process for Sn-Ag-Cu ternary alloy solder bumps, confirmed by characterizing melting temperatures and crystallographic phases. For high-performance system-on-chips (SoCs), the reliability problem of flip chip solder joints is extending from thermal fatigue failure to electromigration failure. As the dimensions of solder bumps shrink, the effects of voids in bumps and crystallographic texture of solder alloys on electromigration resistance must be discussed as well as current crowding. In this work, degassing from Ag/Sn stack-plated bumps has been investigated by thermogravimetry-gas-chromatography/mass-spectrometry (TG-GC/MS). In addition, the texture of electroplated Ag/Sn metal stacks after reflow under different cooling conditions has been characterized by electron backscatter diffraction (EBSD). The experimental results of the gas analyses suggest that the stack-plating process has potentially an advantage of reduction of voids in bumps because of the small amounts of evolved gases from the stacks-plated bumps in comparison with the alloy-plated bumps. From the EBSD results, the Ag/Sn stack as plated has highly [110] oriented /spl beta/-Sn grains nearly parallel to the substrate surface. Under the reflow condition with a cooling rate of 200/spl deg/C/min, the fraction of [110] oriented grains at around 50/spl deg/ angular tilts toward the substrate increases. As the cooling rate of the reflow process is reduced to 50/spl deg/C/min, the strength of the closest-packed [100] texture of /spl beta/-Sn parallel to the substrate surface increases.
収録刊行物
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- 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546)
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2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546) 655-660, 2004-09-28
IEEE