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A defect-tolerant WSI file memory system using address permutation scheme for spare allocation
Description
The authors propose a large capacity high-speed file memory system implemented with wafer scale RAM which adopts novel defect-tolerant technique. The defective memory blocks in the wafer are repaired by switching with the spare ones based on set-associative mapping. In order to repair the clustered defective blocks, these are permuted logically with other blocks by adding some constant value to the input block address. The defective blocks remained even after applying the above two methods are repaired by using error correcting codes which also correct soft errors induced by alpha particles in an on-line operation. With using the proposed technique, the authors demonstrate a large capacity high-speed WSI file memory system implemented with high fabrication yield and low redundancy rate.
Journal
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- Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
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Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems 183-190, 2002-12-30
IEEE Comput. Soc. Press
