説明
To drastically reduce the dynamic power (P/sub AT/) and the leakage power (P/sub ST/), while to keep speed of a CMOS square-root (SR) circuit, a new algorithm, new architectures and a new leakage reduction circuit were developed. Using these techniques, a 90-nm CMOS LSI was fabricated. The P/sub AT/ and P/sub ST/ of the new SR circuit were reduced to about 1/4 and 1/33 those of a conventional SR circuit. Measured results agreed well with simulated results.
収録刊行物
-
- Asia and South Pacific Conference on Design Automation, 2006.
-
Asia and South Pacific Conference on Design Automation, 2006. 90-91, 2006-01-01
IEEE