A Dividing Ratio Changeable Digital PLL Using VCO as Base Clock Source
説明
In this paper, the dividing ratio changeable digital phase locked loop (DCPLL) using the VCO as the base clock source is proposed. In this circuit, the ratio of output jitter is not greatly influenced for the input signal. Also, the lock-in range can be widely compared with the conventional method.
収録刊行物
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- 2009 Fourth International Conference on Innovative Computing, Information and Control (ICICIC)
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2009 Fourth International Conference on Innovative Computing, Information and Control (ICICIC) 1469-1472, 2009-12-01
IEEE