A new high-speed and low-power LSI design of SVD-MIMO-OFDM systems
説明
In this paper, we propose a processor for singular value decomposition (SVD) and compression/decompression of feedback matrices, which is mandatory for SVD multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) systems. The SVD-MIMO is a transmission method, which can suppress multi-stream interference and improve communication quality by beamforming. Because of high calculation cost, any conventional SVD processors are unsuitable for real-time processing. We have employed an application specific instruction-set processor (ASIP) architecture and have realized the high-speed/low-power design and real-time processing by the parallelization of floating point units (FPUs) and arithmetic instructions specialized in complex matrix operations.
収録刊行物
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- 2012 International Symposium on Communications and Information Technologies (ISCIT)
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2012 International Symposium on Communications and Information Technologies (ISCIT) 204-209, 2012-10-01
IEEE
