Highly stable 65 nm node (CMOS5) 0.56 μm/sup 2/ SRAM cell design for very low operation voltage
説明
We show very high density embedded 6T-SRAM cell of 0.56 /spl mu/m/sup 2/. This is the smallest value reported so far. Developed embedded SRAM cell achieves adequate SNM of 90 mV at 0.6 V on high performance 65 nm SoC platform (CMOS5).
収録刊行物
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- 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407)
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2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) 13-14, 2004-03-02
Japan Soc. Applied Phys