Residue signed-digit arithmetic circuit with a complement of modulus and the application to RSA encryption processor
説明
A fast residue arithmetic circuit, using a modulus complement in a signed-digit (SD) number representation, is proposed. For a large modulus M with a length of (p+1) -bit used as a key in an RSA public-key cryptosystem, a complement of M, M*=2/sup p/-M, with the p-digit SD number representation is used to calculate the modular operations. Thus, a modular addition can be implemented by using two SD adders, one for SD addition and another for the modular operation with the complement M*. A modular multiplication is performed by repeating the modular shift and the modular addition operations in a radix-two SD number representation. By using a Booth recording method, the speed of a modular multiplication becomes twice as fast. The circuit design and simulation results by VHDL show that a high speed RSA public-key encryption processor can be implemented by applying the presented residue arithmetic circuit.
収録刊行物
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- 9th International Conference on Electronics, Circuits and Systems
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9th International Conference on Electronics, Circuits and Systems 2 591-594, 2003-06-25
IEEE
