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A CPLD design of a self-organizing system for data clustering
Description
A hardware design of a self-organizing system is presented in this report. A high performance parallel processor is designed with pipeline modules. The size of this system is programmable within a certain degree. In this paper, we design this system using a target CPLD. In addition, this paper shows the error analysis of floating-point operation to estimate the optimum word length of data for the minimization of circuit resources.
Journal
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- ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)
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ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187) 2 441-444, 2002-11-27
IEEE
