A reduction technique of large scale RCG interconnects in complex frequency domain
説明
High frequency digital LSIs usually consist of many subcircuits coupled with multi-conductor interconnects embedded in the substrate. They sometimes cause serious problems in fault switching operations due to time-delays, crosstalk, reflections and so on. In order to solve these problems, it is very important to develop a user-friendly simulator for the analysis of LSIs coupled with interconnects. In our reduction algorithm, we first calculate the dominant poles which make a large contribution to the transient response, and the corresponding residues are estimated by the least squares method. Thus, the interconnect is replaced by an equivalent circuit realizing the partial fractions.
収録刊行物
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- Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.
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Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03. 3 III-490, 2003-11-20
IEEE
