説明
In this paper, the JPEG encoder application, one of the DSP applications, was implemented using the ASIP development system: PEAS-III. Instructions for the JPEG encoder, such as DCT instruction, and butterfly instructions, were added to the initial design. Area, performance, and execution cycles of the processors were calculated using the generated HDL description, compiler, and assembler by PEAS-III. From the experimental results, 12 architectures can be designed in 160 hours, and the designer can select an optimal architecture that satisfies design constraints considering the hardware cost, clock frequency and execution cycles.
収録刊行物
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- 2003 International Conference on Multimedia and Expo. ICME '03. Proceedings (Cat. No.03TH8698)
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2003 International Conference on Multimedia and Expo. ICME '03. Proceedings (Cat. No.03TH8698) I-149, 2003-01-01
IEEE
