A dual layer bitline DRAM array with Vcc/Vss hybrid precharge for multi-gigabit DRAMs
説明
A dual layer BL array and a Vcc/Vss hybrid precharge sensing scheme has been proposed. The array affords the maximum memory cell density and relaxed sense amplifier layout which is as wide as the conventional folded BL sense amplifier layout. The Vcc/Vss hybrid precharge scheme gives the doubled operation voltage for sensing compared with the conventional half Vcc precharge method without the BL charge/discharge current increase.
収録刊行物
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- 1996 Symposium on VLSI Circuits. Digest of Technical Papers
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1996 Symposium on VLSI Circuits. Digest of Technical Papers 190-191, 2002-12-23
Widerkehr & Associates