Optimization methodology of global interconnect structure
説明
The optimal interconnect structure is required because circuit performance depends on resistance and capacitance in interconnects. This paper proposes the optimization methodology of interconnect structure based on the wire length distribution (WLD) model. Using the proposed method, metal height and ILD thickness of global interconnect layer in 65 nm node become larger than the ITRS structure. Compared with the ITRS structure, the delay time can be improved by 9% and 22% for complex and simple circuits, respectively.
収録刊行物
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- Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.
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Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004. 351-354, 2005-06-01
IEEE