Hardware implementations of hash function Luffa
説明
This paper presents hardware architectures for the hash algorithm Luffa, which is a candidate for the next-generation hash standard SHA-3. The architectures were implemented by using a 90-nm CMOS standard cell library. A high throughput of 35 Gbps for a high-speed architecture and a gate count of 14.7 kgate for a compact architecture were obtained. In comparison with Keccak, other SHA-3 candidate in the sponge function category, as well as with the current hash standard SHA-256, Luffa exhibited the advantage of flexible implementation ranging from high-speed to compact circuits.
収録刊行物
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- 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)
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2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) 130-134, 2010-06-01
IEEE