A digital calibration technique for pipelined analog-to-digital converters
説明
A digital calibration technique, which corrects errors due to capacitor mismatch and charge injection in pipelined ADC and directly measures the error coefficient using the ADC INL plot, is described. The proposed technique can be applied for various types of pipelined ADC architectures. Test results using an implemented 10-bit pipelined ADC show that the ADC achieves a peak signal-to-noise-and-distortion ratio of 56.6 dB, a peak integral nonlinearity of 0.3 LSB, and a peak differential nonlinearity of 0.3 LSB using the digital calibration.
収録刊行物
-
- IMTC/2002. Proceedings of the 19th IEEE Instrumentation and Measurement Technology Conference (IEEE Cat. No.00CH37276)
-
IMTC/2002. Proceedings of the 19th IEEE Instrumentation and Measurement Technology Conference (IEEE Cat. No.00CH37276) 1 713-717, 2003-06-25
IEEE