Representation of 3D-LSI floorplan based on stacked-rectangular-dissection
説明
Recently, 3D-LSIs which consist of several silicon layers have been developed and have attracted attention. 3D-LSI has an advantage of the length of wires and the number of components per chip. However, a layout design of the 3D-LSIs will be much complex. In this paper, we propose a stacked-rectangular-dissection, which consists of several rectangular dissections, as a floorplan of 3D-LSI. And to search for a good floorplan of 3D-LSI with simulated annealing, a representation of a stacked-rectangular-dissection is presented.
収録刊行物
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- 2009 IEEE International Symposium on Circuits and Systems
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2009 IEEE International Symposium on Circuits and Systems 1731-1734, 2009-05-01
IEEE