Ferroelectric-Gate Structures and Field-Effect Transistors Using (Bi,La)<sub>4</sub>Ti<sub>3</sub>O<sub>12</sub> Films
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<jats:title>Abstract</jats:title><jats:p>We have fabricated and characterized metal-ferroelectric-metal-insulator-semiconductor (MFMIS) diodes and field-effect-transistors (FETs) using (Bi,La)<jats:sub>4</jats:sub>Ti<jats:sub>3</jats:sub>O<jats:sub>12</jats:sub> (BLT) films. 9-nm-thick SiO<jats:sub>2</jats:sub> is used as an “I” layer. It is shown that the memory window in the capacitance-voltage (C-V) characteristics of the MFMIS structures is as large as 3V for a voltage sweep of 5V, when the area ratio of the MIS region (SI) to the ferroelectric capacitor region (SF), SI/SF, is 15. It is also demonstrated that the MFMIS-FETs using Pt/BLT(150nm)/Pt/SiO<jats:sub>2</jats:sub>(9nm)/Si structures have hysteresis loops due to the ferroelectric BLT film in the drain current-gate voltage (ID-VG) characteristics. Observed threshold voltage shift is 3V and excellent data retention characteristics are demonstrated for the device with an area ratio SI/SF of 15.</jats:p>
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- MRS Proceedings
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MRS Proceedings 688 2001-01-01
Springer Science and Business Media LLC