Manufacturable and reliable fluorine-doped low-k interlayer dielectric process for high performance logic LSI

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説明

Advanced process integration with low-k fluorine-doped interlayer dielectric was presented. Performance improvement due to wiring capacitance reduction was confirmed from speed analysis of inverter delay time by 7%. And it was clarified that there was no influence of fluorine in interlayer dielectric to MOSFET's reliability. This process was carefully optimized from total CMOS integration point of view and was applied to development and production of advanced logic LSI.

収録刊行物

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