The output permutation for the multiple-valued logic minimization with universal literals
説明
This paper shows the effectiveness of an output permutation for the implementation of current-mode CMOS circuits. A combination of a simple function and an output permutation can realize a difficult function and cost for the combination will be lower than the cost for a difficult function. The output permutation can be realized by a universal literal and we can calculate the cost. We first examine the all combinations of universal literals and output permutations and show that some combinations can realize one-variable functions with lower costs. Next, we minimize two-variable functions and compare the costs with the costs obtained by some output permutations. As a result, we show that about 70% functions can reduce the costs and their reduction ratio is about 12% on average.
収録刊行物
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- Proceedings 1999 29th IEEE International Symposium on Multiple-Valued Logic (Cat. No.99CB36329)
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Proceedings 1999 29th IEEE International Symposium on Multiple-Valued Logic (Cat. No.99CB36329) 105-109, 2003-01-20
IEEE Comput. Soc
