A fully integrated 40-Gbit/s clock and data recovery circuit using InP/InGaAs HBTs
説明
An integrated clock and data recovery (CDR) circuit is a key element for optical communication systems at 40 Gbit/s. We present a fully integrated 40-Gbit CDR circuit fabricated using InP/InGaAs HBTs. The circuit contains a linear-type phase detector and a full-data-rate voltage-controlled oscillator. Error-free operation and wide eye opening were obtained for 40-Gbit/s pseudorandom bit sequence (PRBS) with a length of 2/sup 23/-1. The fabricated IC dissipates 1.71 W at a supply voltage of -4.5 V.
収録刊行物
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- 2002 IEEE MTT-S International Microwave Symposium Digest (Cat. No.02CH37278)
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2002 IEEE MTT-S International Microwave Symposium Digest (Cat. No.02CH37278) 83-86, 2003-06-25
IEEE