Heterogeneous 3D integration technology and new 3D LSIs
説明
A new 3-D integration technology and heterogeneous integration technology called a super-chip integration is described. A number of known good dies (KGDs) with different sizes and different devices are simultaneously aligned and bonded onto lower chips or wafer by a chip self-assembly method using the surface tension of liquid in the super-chip integration. Possibilities for new system-on-a chip and heterogeneous LSIs by 3D super-chip integration such as 3D stacked multicore processor with self-test and self-repair function, GPU stacked 3D image sensor with extremely fast processing speed and 3D stacked reconfigurable processor with spin memory are discussed.
収録刊行物
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- 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology
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2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology 1-4, 2012-10-01
IEEE
