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Fully integrated embedded DRAM technologies with high performance logic and commodity DRAM cells for system-on-a-chip
Description
This paper demonstrates a process integration for high performance and small footprint embedded DRAMs. A trench capacitor cell and a self-aligned bit line contact are selected to maintain exactly the same size as commodity DRAM cells. The cell array region is covered with a thin SiN barrier against salicidation. Ti-salicide source/drain is used in the logic region. No retention time degradation and good circuit performance are confirmed.
Journal
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- 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)
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1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) 243-246, 2003-01-20
IEEE
