Logical function and delay time extraction from MOS circuit data

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Description

An algorithm to extract logical function and delay-time from CMOS circuit-level data is proposed. The resultant data from this algorithm is a logic-level circuit description. It is applied to conventional logic simulators. As a result, a large circuit can be simulated at once, and the time needed for simulation and verification is saved. The algorithm consists of three parts, network partitioning, extraction of logical function, and extraction of delay time. >

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