A floating body cell (FBC) fully compatible with 90nm CMOS technology(CMOS IV) for 128Mb SOI DRAM

Mutsuo Morikado, A. Sakamoto, Naoki Kusunoki, Takeshi Hamamoto, Hiroomi Nakajima, Kosuke Hatsuda, K. Inoh, Takashi Ohsawa, Hiroyoshi Tanimoto, Katsuyuki Fujita, Tomoki Higashi, Yoshihiro Minami, Tomoaki Shino, Akihiro Nitayama, Nobutoshi Aoki

doi:10.1109/iedm.2005.1609336

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A floating body cell (FBC) fully compatible with 90nm CMOS technology(CMOS IV) for 128Mb SOI DRAM

DOI

Mutsuo Morikado
A. Sakamoto
Naoki Kusunoki
Takeshi Hamamoto
Hiroomi Nakajima
Kosuke Hatsuda
K. Inoh
Takashi Ohsawa
Hiroyoshi Tanimoto
Katsuyuki Fujita
Tomoki Higashi
Yoshihiro Minami
Tomoaki Shino
Akihiro Nitayama
Nobutoshi Aoki

説明

A 128Mb SOI DRAM with FBC (floating body cell) has been successfully developed for the first time. Two technologies have been newly implemented. (i) In order to realize full functionality and good retention characteristics, the well design has been optimized both for the array device and the peripheral circuit. (ii) Cu wiring has been used for bit line (BL) and source line (SL), which leads to increasing the signal of the worst bit in the array and also realizes the full compatibility with 90nm CMOS technology