A floating-gate-MOS-based multiple-valued associative memory
説明
A digit-serial, multiple-valued associative memory VLSI for high-speed information search is presented. Input and output data of a processing element (PE) in the VLSI are directly encoded by appropriate multiple-valued digits, respectively, so that search operations are efficiently described by the combination of a multiple-valued down literals and pass gates. Moreover, multiple-valued memory information is stored in each PE by programming the threshold of the down literal which can be easily implemented using special MOS transistors, called floating-gate MOS transistors. It is demonstrated that the number of interconnections and transistors in the 5-valued associative memory can be reduced to 25% and 53%, respectively, in comparison with the corresponding binary implementation. >
収録刊行物
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- [1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic
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[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic 24-31, 2002-12-10
IEEE Comput. Soc. Press
