A 1.9 ns BiCMOS CAM macro with double match line architecture
説明
A 64-entry*32-b high-speed BiCMOS CAM (content addressable memory) macro is implemented on a 0.5 mu m BiPNMOS sea-of-gates. In order to realize high-speed operation, a double match line (DML) architecture and a BiCMOS pull-up circuit are employed. The BiCMOS pull-up circuit imparts high drivability to a second match-line driver. A fabricated chip shows 1.9 ns of address-to-match delay time. The CAM macro also has high-density characteristics because a single CAM cell occupies only one basic cell of the gate array. Since the CAM macro is implemented on a gate array, the configuration can be altered easily and quickly depending on customers' requests. >
収録刊行物
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- Proceedings of the IEEE 1991 Custom Integrated Circuits Conference
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Proceedings of the IEEE 1991 Custom Integrated Circuits Conference 14.3/1-14.3/4, 2002-12-09
IEEE