Embedded SRAM and Cortex-M0 Core with Backup Circuits using a 60-nm Crystalline Oxide Semiconductor for Power Gating

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Description

Using data retention circuits that include crystalline oxide semiconductor transistors as backup circuits for power gating, a processor system can reduce standby leakage current significantly. This is effective in the Internet of Things (IoT) applications that require standby power reduction. The crystalline oxide semiconductor transistor can constitute a nonvolatile data retention circuit easily because it exhibits significantly lower off-state current than a silicon transistor and is highly compatible with a CMOS logic circuit. The backup circuit can achieve 2-clock-cycle data backup and 4-clock-cycle data restore; thus, the processor system can efficiently perform temporally fine-grained power gating and can achieve longer standby times. Furthermore, area overheads due to the backup circuits are kept very small because the crystalline oxide semiconductor transistors are stacked on silicon transistors.

Journal

  • IEEE Micro

    IEEE Micro 1-1, 2015-01-01

    Institute of Electrical and Electronics Engineers (IEEE)

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